“Today, most CSP plants use a steam cycle. One of the advantages of the CO2 cycle over the air cycle is that it's higher efficiency than steam, but performs at much lower temperatures than needed with an air Brayton cycle as used in a gas turbine,” says NREL's Craig S. Turchi, PhD, Concentrating Solar Power Program. “That overlap of better efficiency than steam and also lower temperatures is completely relevant for power towers, and even for troughs in some cases.”
The technology is based on a closed-loop Brayton cycle. It starts off compressing CO2 to very high pressure. “Unlike a gas system, this is a high pressure system – but a relatively low pressure ratio. The compressor takes the gas from around 70 Bar and it will pressurise it up to about 200 to 250 Bar. Then this high pressure CO2 is heated and, in our case, we take run it directly into a solar receiver or heat exchange it with molten salt to get very high pressure, high temperature CO2.”
At that point, it is expanded through the turbine. “It's that turbine technology that is the challenge this project is trying to address. That has never been done at commercially feasible sizes yet,” Turchi explains.
The testing will be done at Sandia National Labs nuclear test users facility (NTUF). “Building a cycle of this size has been on their goal list for a number of years. But they haven't been able to put funding together to support a test of this size until this project came along. They are a major partner for us,” says Turchi.
“Based on the thermodynamics of using CO2 instead of steam, we predict it will add several percentage points in efficiency,” he continues, explaining that if a modern steam Rankine power tower is running at 41–42% efficiency in a dry-cooled configuration, for example, “we think with the s-CO2 cycle, we can push that up to around 45% efficiency and even further as the technology matures”.
Solar PV R&D: what are researchers working on?
About: Joyce Laird has an extensive background writing about the electronics industry; semiconductor development, R&D, wafer/foundry/IP and device integration into high density circuit designs.